The present invention is in the field of adding 4:2 compressors functions to programmable logic devices. In particular, the present invention arranges 3:2 compressors to form 4:2 compressors, while both allowing the use of the arithmetic capabilities of the compressors, and also logic combinations that can be implemented by 3:1, 3:2, 4:1, and 4:2 LUT (look up tables).
In one conventional arrangement, to add together multiple operands, the operands are added together two at a time, in a so-called adder tree. For example, to add together four operands using such an arrangement, two of the operands are added together to obtain a first intermediate result, and the other two operands are added together to obtain a second intermediate result. Then the first and second intermediate results are added together to obtain a final result. Typically, in this arrangement, a ripple carry adder or a carry propagate adder is used for each addition. In a ripple carry or carry propagate adder, two numbers in binary form are added together, with one number as a result. Most programmable logic architectures support ripple carry addition for adder trees, as the number of inputs and outputs between the local logic and global routing architecture is relatively small. (2 inputs, 1 output per result bit). Also, most programmable logic architectures have a n−1 logic cell structure. (3 or 4 inputs, 1 output bit).
In another conventional arrangement, in an initial step, three of the four operands are added together bitwise using a carry-save adder. The resulting sum and carry for each bit are provided to a second stage carry-save adder which adds in the fourth of the four operands and generates a sum and carry bit for each operand. Finally, a carry-propagate adder adds together the sum and carry result bits from the second stage carry-save adder to generate the sum of the four operands. However, 3:2 compressors are inefficient when implemented using PLD architectures. That is, because of the two outputs, two LUTs are burned per level. 4:2 compressors are more efficient, because they have the same routing density of ripple carry adders (2:1 input/output ratio).
However, routing must be provided between the 3:2 compressors (which is inefficient in PLDs) to build a 4:2 compressor.